This work proposes a novel CMOS capacitance detector, leveraging cross-coupled topology to simultaneously achieve fast response times and capacitance resolution as low as a zepto-farad. Another distinguishing specification is that the proposed architecture relies on dynamic supply voltage, resulting in zero static power consumption. The outstanding performance of the introduced structure is verified by post-layout simulations in a 180 nm CMOS process. Owing to its unique construction, the proposed design benefits from a high resolution of 1 zF and offers an IDR range of 10 fF
